Amazon Kindle D00111 Uživatelský manuál stáhnout pdf (Strana 35)

7 E-Book Demo Hardware

7.1 Display technology

Before commencing work on the hardware, we had to choose a suitable E-paper screen

technology that is tested, reliable and yet robust. The screen technology of choice was the E-

Ink because it was easier to obtain, moreover both earlier versions of E-Readers and present

ones are using it. It is worth emphasizing that the E-paper industry is still in its infancy, which

also implies that there are a few infrastructures in place to manufacture E-papers compared to

LCD or CRT. Every E-paper manufacturer must also manufacture its own device-controller

including other hardware that must be tailored to its own specific device. LCD-technology, on

the other hand, is well established and is ported on almost all CPU and micro-controller in the

market.

The aforementioned constraints implies that it is very difficult to obtain an E-paper display

and even when you obtain one, the company that provides it must also provide the necessary

device-controllers to convert the LCD port on the CPU or micro-controller to fit an E-paper

display. These difficulties left us with only one option, which is a development kit.

7.2 Description of the Board

The development kit is built around Samsung S3C2410-ARM9 CPU. The CPU is based on

Reduced Instruction Set Computer (RISC) architecture with 32-bit-word. The CPU provides

64-way set-associative cache with Instruction Cache (16KB) and Data Cache also (16KB)

[48]. With these features, the CPU operates at a speed of 203MHz, which is good enough for

most hand-held devices, including an E-Book-Reader.

According to Hennessy and Patterson [52], a CPU with a 16KB Instruction Cache and 16KB

Data Cache will outperform a 32KB Unified Cache. The average memory access time is given

Average memory access time = Hit time + Miss rate x Miss penalty

Where, “Hit time is the time to make a hit in the cache, Miss rate is number of cache accesses

that misses divided by number of accesses, Miss penalty is the number of cache misses and

the miss per cost"[52]. Consequently, two separate caches in the Arm9, enhances performance

through parallelism. For example, if there is a stall in the CPU because of a miss in the Data

Cache, by virtue of parallelism the next eligible instructions in the instruction cache will be

executed. Without being too overly optimistic the overall result is a faster CPU.

CPU Samsung Arm9 203MHz

Screen E-Paper (E-Ink technology)

Size: 5 Inches

Resolution: 600*800 pixel, 4 grayscale

Pixel Pitch: 0.151(h)x0.153(v)

Pixel Configuration: Rectangle

Active Area: 90.6 x 122.4 mm (5”)

Display Thickness: 1.5mm

Display Weight: 35g

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Amazon Kindle D00111 Uživatelský manuál Strana 35